1. Field of the Invention
The present invention relates to frequency tracking in fractional-N phase-lock-loops (PLLs) and more specifically to the generation of a low-power fractional compensation pulse used in the suppression of spurious sidebands in these PLL circuits.
2. Brief Description of the Prior Art
Fractional-N synthesizers have become popular in many wireless transceiver applications due to their good RF performance. Standards such as GSM, IS-136, PHS, and PDC are all based on time division multiple access (TDMA) techniques, where low phase noise and fast switching from one channel to another is imperative to meet system sensitivity and time-slot requirements.
FIG. 1 shows a typical architecture for the conventional type integer-N PLL used predominantly in the wireless market today. In this conventional scheme, N is an integer number. In this circuit, the reference frequency .function..sub.R, which is divided down by reference divider 2 from the crystal 1, drives the phase frequency detector (PFD) 3 as does the feedback signal .function..sub.v, which is the output frequency .function..sub.o from the voltage controlled oscillator (VCO) 6, divided by integer N in the main divider 7. The output of the charge pump 4 is coupled to filter 5 to provide a dc voltage to the VCO 6. In conventional type PLL synthesizers, the phase frequency detector (PFD) comparison frequency must be equal to the channel spacing because the main divider can only increment or decrement in integer steps; i.e., EQU .function..sub.o =N.multidot..function..sub.R, and Eq. 1 EQU .DELTA..function..sub.o =.function..sub.ch =.function..sub.R. Eq. 2
On the other hand, the main divider in a fractional-N synthesizer, shown in FIG. 2, is capable of generating steps in fractions of the comparison frequency, so that EQU .function..sub.o =N.sub.eff.multidot..function..sub.R Eq. 3
where the total effective division ratio, N.sub.eff, is given as ##EQU1## ##EQU2## PA1 m=2.sup.L is the maximum count for the accumulator. PA1 in dBc/Hz.
represents the fractional portion of the equation and is produced by incrementing an L-bit accumulator in a continuous fashion by x amount at the reference rate up to the maximum count m.
In this circuit, the L-bit accumulator 8 will overflow at the rate of ##EQU3##
The circuit for the fractional-N synthesizer looks much like that for the integer-N synthesizer discussed above, but now the main divider 7 is capable of switching from divide by N to divide by N+1 based on the overflow conditions of an L-bit accumulator 8. As a result the channel spacing is related to the comparison frequency .function..sub.R as N or x changes for a specific m as ##EQU4##
The principle of operation for the fractional-N synthesizer is based on the fact that the main divider 7 will divide by N while the L-bit accumulator 8 is incrementing until an accumulator overflow occurs, at which point the main divider 7 will divide by N+1, resulting in the N.sub.eff fractional division ratio given in Eq. 4. From Eqs. 2 and 6 it is seen that the comparison frequency in fractional-N PLL synthesizers is m-times higher than in the conventional integer-N synthesizer and from Eq. 3 it is seen that for a constant RF output frequency, .function..sub.o, this higher comparison frequency will result in a lower division ratio, N.sub.eff.
It is well known in the art that in a PLL based system with constant PFD phase noise (.English Pound.), the so called "close-in noise" (the synthesizer noise floor within the loop bandwidth) is directly proportional to the division ratio, so that EQU .English Pound.=PFD(phase noise)+20 log(N), Eq. 7
Therefore, reducing the division ratio N.sub.eff by adopting fractional-N techniques, as discussed above, results in lower phase noise in the synthesizer. In addition, the higher comparison frequency in the fractional-N type synthesizer provides faster switching times since the loop bandwidth can be made wider as a result of the comparison spurs being further out in the spectrum. For example, in a modulus 8 (m=8) fractional-N synthesizer there is a phase noise improvement of EQU 20 log(m)=20 log(8)=18 dB, and Eq.8
for a channel spacing of 30 KHz, the comparison frequency is increased to EQU .function..sub.n =.function..sub.ch.multidot.m=30.multidot.8=240 Khz. Eq. 9
The timing diagram for a fractional-N synthesizer with m=8 and x=2 is shown in FIG. 3. Because the main divider 7 operation is integer in nature but on average a fractional part is introduced due to the switching from divide by N to divide by N+1, the output of the main divider 7, .function..sub.v, is phase modulated with a fractional-N phase ripple. Unfortunately, this phase ripple shows up at the output of the phase detector and results in pulse width modulated (PWM) current, I.sub.cp, out of the charge pump 4. If left uncompensated, this ripple current produces sideband energy in the output VCO spectrum which is considered the major problem with fractional-N PLL synthesizers.
FIG. 4 shows a fractional compensation circuit that compensates for this PWM phase ripple in the I.sub.cp current and significantly reduces the magnitude of the fractional-N sidebands. In this case, the PWM phase ripple is proportional and synchronized to the contents of the L-bit fractional accumulator 8, and as a result can be used to control the fractional-N sideband compensation pulse amplitude. In this circuit, fractional timing circuitry 11, a fractional charge pump 10 and a digital to analog converter (DAC) 9 are added to the conventional-N PLL circuit. The fractional pulses, which are driven at a constant rate from the crystal 1, have constant width and their amplitude is modulated. The content of the L-bit accumulator 8 is feed through a digital-to-analog converter (DAC) 9 and used to modulate the amplitude of the compensation current (I.sub.comp), which is generated by the fractional charge pump 10. Special fractional timing circuitry 11, running at a fixed frequency from the crystal 1 and controlled by the .function..sub.v signal from main divider 7, generates the fixed-width fractional compensation pulse which in turn drives the fractional charge pump 10. The theory is that the PAM output from the fractional charge pump 10 cancels the spurious PWM signals from the main charge pump 4.
FIG. 5 shows the relationship between the I.sub.cp (PWM) pulse, the I.sub.comp (PAM) pulse, the fractional compensation pulse T.sub.FP, and the accumulator count. To properly minimize the fractional-N sidebands in the VCO spectrum, it is essential that the area under the main charge pump 4 pulse (I.sub.cp), which represents the amount of charge delivered to the loop filter, is equally matched to the area of the fractional charge pump 10 pulse (I.sub.comp). The fractional timing circuitry 11 provides a fractional compensation pulse which is precisely positioned such that it always encloses the short current pulses of the main charge pump, I.sub.cp This compensation method works effectively for single band applications, but due to the fixed width of the compensation pulse which is driven from the fixed frequency crystal, it is ineffective for dual-channel or multi-channel operation.